As dynamic random access memory (DRAM) devices become more highly integrated, the area available for each memory cell is reduced. Accordingly, the substrate area available for each memory cell capacitor may be reduced so that it may be difficult to maintain a desired memory cell capacitance as integration densities increase. Reduced memory cell capacitances may lower the reading capacity of the memory cell, increase a soft error rate (SER), and/or degrade the memory cell operation at low voltages. Accordingly, there exists a need to provide a memory cell capacitor occupying a reduced surface area of the memory device substrate while maintaining a desired capacitance.
In response, capacitors having three-dimensional structures have been proposed to increase the surface area of the capacitor electrodes thereby increasing the capacitance of the resulting capacitor. In particular, a cylindrical electrode structure has been discussed wherein the inner and outer surfaces of a cylinder are used to increase the effective capacitor electrode area.
Capacitor electrode surface areas have also been increased using hemispherical grained silicon (HSG-Si) layers on the surface of a capacitor electrode. The hemispherical grained silicon layer increases the surface area of the capacitor electrode by providing a roughened surface thus increasing the memory cell capacitance. It may be difficult, however, to form a hemispherical grained silicon layer on the surface of the cylindrical capacitor electrode as discussed below.
First, it may be difficult to provide a desired conductivity for the hemispherical grained silicon layer if the thickness of the hemispherical grained silicon layer is too great. In particular, the hemispherical grained silicon layer may be formed in an undoped state. Accordingly, the hemispherical grained silicon layer is preferably doped with a dopant such as phosphorous to provide the conductive capacitor electrode. In particular, the hemispherical grained silicon layer can be deposited and then dopants can be diffused from the cylindrical polysilicon electrode to the hemispherical grained silicon layer thereon. The capacitance of the resulting capacitor may thus be closely related to the doping concentration of the hemispherical grained silicon layer. In other words, the memory cell capacitance may increase with increased doping concentrations of the hemispherical grained silicon layer.
In the case of the cylindrical capacitor electrode, however, the hemispherical grained silicon layer may be formed on the inner and outer surfaces of the electrode. Accordingly, the hemispherical grained silicon layer may be insufficiently doped if the hemispherical grained silicon layer is too thick. There may thus be practical limits to the thickness of a hemispherical grained silicon layer to maintain a desired conductivity.
Second, the use of a hemispherical grained silicon layer on a cylindrical capacitor electrode may result in damage to the cylindrical capacitor electrode. In particular, a conductive bridge may be formed between neighboring capacitor electrodes when forming the hemispherical grained silicon layer. Accordingly, any bridging between capacitor electrodes should be removed to prevent electrical shorts between the respective memory cells. These bridges are commonly removed using an etch-back step. This etch-back step, however, may damage the cylindrical storage electrodes thereby reducing an effective surface area thereof.
Accordingly, there continues to exist a need in the art for improved methods of forming memory cell capacitors.